1. Field of the Invention
The present invention relates to a method for producing a circuit board layer (circuit level), for an in particular multilayer circuit board, a ceramic foil having a carrier foil disposed on it being used.
2. Description of Related Art
The constantly progressing miniaturization and continuously increasing complexity of electronic circuits require the production and use of multilayer circuits, that is, circuits in which circuit components are disposed on a plurality of levels and are combined into one functional unit. In the related art, ceramic multilayer circuits are known for this purpose, which are made up of flexible, ceramic, so-called blank foils, which are made up of organic binding agents, solvents, and inorganic components. Two process stages may be roughly distinguished in the current process flow for producing the multilayer circuit in the multilayer ceramic design, that is, the co-fire process and the post-fire process, the co-fire process describing the processing in the blank state and the post-fire process describing the processing in the ceramic state. In the first process stage, the co-fire process, the process sequence common in the related art is designed such that the ceramic blank foils are mounted on a carrier medium, and a patterning of the circuit is performed by stamping the blank foils, that is, a mechanical process step, as a function of the design of the circuit for the product in which the circuit is to be used. In particular, the individual circuit paths, that is, circuit traces, for example, are created in this process. Then, feedthroughs, so-called vias, are printed with the aid of a pattern representing one of these vias or with the aid of such a screen, which means that the holes stamped as vias are filled with electrically conductive thick-film paste with the aid of a screen-printing technique. Then, the blank foil on which vias are printed is dried. Subsequently, circuit traces are printed on the blank foil with the aid of an additional, different pattern; the pattern used in this instance renders the print image of the circuit traces. Subsequently, the blank foil on which vias and circuit traces are now printed is dried again. In the next processing step, a plurality of blank foils produced in this manner are stacked and laminated, which results in the laminate of the multilayer circuit. Subsequently, the blank foils or the laminate are sintered as a whole, and this results in the ceramic multilayer circuit. This requires a plurality of process steps, which in particular are highly susceptible to dimensional discrepancies and positional discrepancies between individual method steps, for example, of the printing processes with regard to the feedthroughs (vias) and the circuit traces, in which extremely high dimensional accuracy requirements must be satisfied. Another disadvantage of this process is that a plurality of differently designed or equipped machines must be used for different processing steps in the mass production; moreover, a high occupation of buffer spaces for drying and intermediate storage periods, for example, is a disadvantage. It is also a disadvantage that in particular after the stamping and printing processes respectively a quality control has to take place in order to be able to satisfy the required dimensional accuracies. The circuit trace spacings and via diameters cannot be miniaturized at will using the process technology known in the related art; at present, there are limitations with regard to this miniaturization of approximately 80 μm for via diameters and of approximately 130 μm for the circuit trace width. This prevents an even more compact design of the multilayer circuits.